Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms

The ever-increasing need for securing computing systems using cryptographic algorithms is spurring interest in the efficient implementation of common algorithms. While can be implemented software base instruction sets, there considerable potential to reduce memory cost and improve speed specialized instructions associated hardware. However, a assess benefits costs implementations new that implement key fewer cycles. primary aim this paper understanding performance implementing RISC-V set architecture (ISA) two cases: rv32i supported by dedicated hardware additional functional units. For both cases, we describe processor with cryptography extensions hand-optimized assembly language eleven Compared only set, extension provide 1.5× 8.6× faster execution 1.2× 5.8× less program five Based on our analyses, proposed increase efficiency